1. Field of the Invention
The present invention relates to a computer readable medium and an exposure method.
2. Description of the Related Art
To manufacture semiconductor devices by photolithography, projection exposure apparatuses are used which project a circuit pattern drawn on a mask (or reticle) onto a substrate such as a wafer via a projection optical system, thereby transferring the circuit pattern. Recent advanced microfabrication technologies for semiconductor devices require improved resolutions (higher resolutions) of the projection exposure apparatuses.
Increasing the NA (Numerical Aperture) of the projection optical system and shortening the wavelength of exposure light are conventionally known means for achieving a higher resolution of a projection exposure apparatus. RET (Resolution Enhanced Technology) is also attracting attention, which improves the resolution of a projection exposure apparatus by reducing a k1 factor (also called a “process constant”).
As the k1 factor becomes smaller, exposure becomes more difficult. In prior arts, exposure (e.g., exposure conditions and exposure method) is optimized by repeating experiments several times and confirming the possibility of exposure (i.e., whether it is possible to faithfully project the circuit pattern). However, the difficulty level of exposure has now risen, and experiments to confirm the exposure possibility waste time and cost. Instead, exposure is optimized presently by repeating exposure simulations using a computer. The mainstream of such simulations is so-called model-based RET which performs simulations based on physical models of optics from simulations based on predetermined rules.
The model-based RET generally uses partially coherent imaging calculation. When the partially coherent imaging calculation speeds up, the time required for the model-based RET (simulations) shortens. In the current advanced computer environments, a technique of increasing the calculation speed by parallelizing a plurality of computers has been proposed. Another proposal is a technique of speeding up calculations more effectively by improving the algorithm to execute the partially coherent imaging calculation than by computer parallelization.
For example, Cris Spence, “Full-Chip Lithography Simulation and Design Analysis—How OPC is Changing IC Design”, Proc. of SPIE, USA, SPIE press, 2005, Vol. 5751, pp. 1-14 (reference 1) reports that the SOCS algorithm has increased the calculation speed (simulation speed) by 10,000 times. Alfred Kwok-kit Wong, “Optical Imaging in Projection Microlithography”, USA, SPIE press, 2005, pp. 151-163 (reference 2) describes the partially coherent imaging calculation but presents no algorithm for realizing a calculation speed more than that of the SOCS algorithm. Note that the SOCS is called Coherent Decomposition in reference 2.
However, the SOCS takes time to calculate a TCC (Transmission Cross Coefficient) or decompose an eigenvalue and eigenfunction.